The present invention relates to power devices, more particularly to the design and fabrication of diodes.
The diodes are commonly used in both low and high frequency applications. For low frequency applications, the “slow” diodes, such as, rectifier diode, are used. The slow diodes generally are formed without adding any local lifetime control elements. However, for high switching frequencies, e.g., for use with power switches such as Insulated Gate Bipolar Transistors (IGBT), the “fast” diodes are used. These fast diodes can be obtained by varying the doping profiles and local lifetime control. Local lifetime control is achieved either by exposing the diode to ion beams (helium) or by doping with heavy-transition metals (gold or platinum).
Planar diffusion technology is widely used for the fabrication of power devices. Planar diffusion process selectively introduces dopant into the semiconductor surface by using either an oxide layer as a mask against dopant diffusion or by using a photoresist layer to block the dopant during ion implantation.
FIG. 1 shows a conventional diode 100. The diode includes an N− silicon layer 101 with low doping concentration, an N+ silicon region 102 with high doping concentration, and a cathode 105 that is in contact with the N+ region 102. The N+ region 102 can be a substrate of an epi-wafer or a diffused layer. The front side of the diode includes a P+ doped emitter region 103 and an anode 106 that contacts the emitter region 103. A channel stopper 104 is formed at an edge 113 of the die and is typically an N+ region. In diodes that are designed for higher blocking voltage, e.g., 600 volts or more, the emitter region 103 is surrounded with one or more guard rings 107. A passivation layer 108, e.g., thermal oxide, is formed on the upper surface of the N− layer 101 and the emitter region 103. Generally, the thermal oxide is used when the passivation layer is formed directly on the silicon.
The emitter region 103 is formed by selectively diffusing the P-type dopants into the N− layer 101. As a result, the diffusion window has a substantially planar region or parallel plane 109 at the P-N junction between the emitter region 103 and the N− layer 101. Since the dopants also diffuse laterally, the diffusion window also has a curved edge 110 with a radius that is 80-90% of the vertical junction depth, depending on the dopant concentration of the emitter region.
During the reverse bias condition, the breakdown voltage of the planar P-N junction is limited due to the curvature effect associated with the curved edge 110. One method of increasing the breakdown voltage is to reduce the electric field at the main junction, e.g., at the curved edge 110, by using one or more guard rings 107. The term “floating field rings (FLR)” is also used to refer to the guard rings since these rings include diffused regions that are isolated from the main junction and provided at close proximity thereto. The main junction refers to the P-N junction defined by the emitter region (or P region) and the N− region. Typically, these guard rings or FLRs are formed using the same processing step used to form the emitter region 103, i.e., by creating extra implantation windows in the mask that surrounds the emitter region 103.
When a reverse bias voltage is applied to the cathode 105 of the diode, the depletion layer that is initially associated with the main junction extends outward with the increase in the reverse bias voltage. The first ring 107 is provided at a given space from the main junction so that punch-through takes place before the avalanche breakdown voltage occurs at the main junction, thereby limiting the maximum electric field across the main junction. A further increase in the reverse voltage is shared with the first ring until the depletion layer punches through to the adjacent second ring. Therefore, the FLR structure acts like a voltage divider minimizing the electric field at the edges of the main junction, and the breakdown voltage increases to the 90 percent of plane parallel or ideal breakdown voltage.
For the field ring structure to be effective, the spacing between the rings should be individually optimized to prevent the avalanche breakdown. If the rings are not provided with proper spacing, the rings can suffer from surface instabilities caused by high electric fields and charges generated during the formation of the passivation layer 108. The surface or passivation charges can cause a variation in the surface potential and create surface channels on the lightly-doped region between the rings, which would result in leakage current. This alters the potential sharing between the rings, and the device breakdown may occur when there is excess charge due to increase in the electric field.
FIG. 2 illustrates a diode 200 having a plurality of metal field plates 211. The metal field plates are used to reduce the charges (“passivation charges”) associated with the formation of the passivation layer. The diode 200 includes an N− silicon layer 201 with low doping concentration, an N+ silicon region 202 with high doping concentration, and a cathode metal 105 that contacts the N+ region 202. The N+ region 202 is typically a substrate of an epi-wafer or a diffused layer. The front side of the diode includes a P+ doped emitter region 203 and an anode 206 that is in contact with the emitter region 203. The emitter region defines a diffusion window that has a substantially planar region (or parallel plane) 209 and a curved edge 210.
A channel stopper 204 is formed at the edge 213 of the die and is typically an N+ region. A plurality of guard rings 207 surrounds the emitter region (or main junction). A first passivation layer 208 is formed on the upper surface of the N− layer 201 and the emitter region 203. A second passivation layer 212 is formed on the first passivation layer and the metal field plates to prevent arcing between the metal plates. The second passivation layer may be made of polyimide or silicon nitride.
Even with the guard rings and the metal plates, it is difficult to obtain a 100%-planar-region breakdown voltage due to the curvature effects of the curved edge 210. In addition, for fast diodes or FREDs that are doped with platinum or gold, the channel stopper needs to be designed, so that the depletion width does not go underneath the channel stopper and touch the die edge 213 since that would result in channeling current.
FIG. 3 illustrates the curvature effects of the curved edge 210 of the diode 200. The current and voltages concentrate at the curved edge 210 more so than the planar region 209. Such a phenomenon presents an even more challenge in diode development with the introduction of the switching transients with very high di/dt and dv/dt conditions since the static current density at the curvature junction may crack or burn out the silicon depending upon the crystal orientation.
FIG. 4 illustrates a diode 400 configured to reduce the current density at the curvature. A small resistor 414 (or resistance value) is provided in the emitter region. If this series resistance is sufficiently small, e.g., 3 ohm, the diode does not burn since the voltage drop across the series resistor helps in reducing in the current density at the curvature junction. However, designing such a small series resistance into the emitter region tends to be a difficult task.